How it works

The purpose of this device is to produce a  controlled number of picosecond SFQ pulses at the output “OUT” when a slowly changing DC current is applied to the input “IN”.  The device is build around a DC SQUID J2-L8-{J3,J1} (junctions J1 and J3 act as a single junction). When the input current is increased above a certain value, the dc current through junction J2 exceeds the critical value and the junction flips, generating a flux-antiflux  pair. The flux quantum moves  to the output, while the antiflux is captured in the quantizing loop of the SQUID.  This immediately changes the dc current inside the SQUID (approximately,  by F0/L8) and the  current through junction  J2 is  reduced below the critical value. The net result  is that a single picosecond SFQ pulse can be generated  on-chip by applying a slowly changing,  noisy and inexact (within the F0/L8 = 0.5 mA window) dc current from a room-temperature current source. Similarly, when the input current is decreased below a certain value, the split junction {J1,J3} flips, restoring the initial state of the SQUID. Junction J4 is optional, it serves as a one-stage output JTL to sharpen the SFQ pulse (compare the J2 and J4 waveforms below) and to match the output of the DC/SFQ converter with the load.

The device was simulated and optimized with a current source and a resistor at the input and a resistive load at the output:

 

References

The  device is very similar to the one described in:

V. K. Kaplunenko, V. P. Koshelets, K. K. Likharev, V. V. Migulin, O. A. Mukhanov, G. A. Ovsyannikov, V. K. Semenov, I. L. Serpuchenko, and A. N. Vystavkin, “Experimental Study of the RSFQ Logic Circuits,” in: Extended Abstracts of ISEC’87, Tokyo, pp. 127-130, Aug. 1987. K. Likharev and V. Semenov,  “RSFQ logic/memory family: A new josephson-junction technology for sub-terahertz clock-frequency digital systems”,  IEEE Trans. Appl. Supercond., vol. 1, pp. 3-28, March 1991.

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