How it works

This is a T flip-flop-based NDRO (Non Destructive Read Out) cell. “A” is the toggle input of the T flip-flop, formed by junctions J1-J2-J3-J4-J5-J7 (J1 and J2 act as a single junction, J7 is a single stage output JTL). The quantizing inductance of the T flip-flop is formed by L7+L5+L4+L13. Note that output “C” follows the “0” -> “1” transitions of the T flip-flop. Junctions J9, J10 and J12 (directly connected to the quantizing inductance) are the key element of the design, allowing a non-destructive read-off of the internal state of the T flip-flop. When the T flip-flop is in state “0” (no flux quantum inside) junction J12 is biased well below the critical value, so that when a read-out SFQ voltage pulse appears at the “NR” input, it induces a 2*Pi phase leap in buffer junction J11, while J12 (as well as J9, J10) preserves its state. As a result, no output is produced at pin “S” and, therefore, the “0” state of the T flip-flop is successfully read out. When T flip-flop is in state “1”, junctions J9 and J12 are baised closer to their critical values so that an SFQ pulse at input “NR” flips junctions J8, J12, J13 and J14. As a result, we have an output SFQ pulse at pin “S”. Junction J9 also flips during the read out of “1”, compensating for the phase change across J12. Junction J10 flips when the state of the T flip-flop changes from “1” to “0” (i.e., when junctions J1, J2 and J4 flip), preventing accumulation of flux in the loops J2-L8-L5-L10-J9-J10-J12 and J7-L11-L4-L10-J9-J10-J12. It is instructive to compare this cell to its close relative – SFQ/DC converter.

References

O. A. Mukhanov, S. V. Rylov, V. K. Semenov, and S. V. Vyshenskii, “RSFQ Logic Arithmetics,” IEEE Trans. Magn., vol. MAG-25, No. 2, pp. 857-860, Mar. 1989. K. Likharev and V. Semenov,  “RSFQ logic/memory family: A new josephson-junction technology for sub-terahertz clock-frequency digital systems”,  IEEE Trans. Appl. Supercond., vol. 1, pp. 3-28, March 1991.