T flip-flop

Schematic

Unless otherwise stated, all parameters here and below

are in PSCAN units (for 3.5 um).

Moore diagram

How it works

The operation of this latch is identical to that of an RS
flip-flop (trigger) with joined set and reset inputs.

T flip-flop has 2 stable states: “1” and “0”, that is, with and without
a magnetic flux quantum stored inside the loop LPJ4 – J4 – L7 – L4
– L6 – J3 – LPJ3. Every input pulse “T” triggers switching of the latch
to the opposite state. When it is in state “0” an incoming SFQ pulse at
port “T” flips junctions J0, J4 and J1 and thus switches the T flip-flop
to the state “1”. When the latch is in state “1” an SFQ pulse at input
“T” flips junctions J0, J2 and J3 and returns the flip-flop to state “0”.
The transition “1” -> “0” results in appearance of an SFQ pulse at the
output “QN” (junction J3). Note that the frequency of the of the output
pulses is exactly 1/2 of the frequency of the input pulses.

Junction J0 is optional and serves as a one-stage matching JTL. Due
to bipolar dc biasing scheme (note the dc current drain IA) this particluar
version has an unusually wide parameter tolerance band.

The latch was simulated and optimized as an array of 3 identical T flip-flops
with special JTLs at the input and the output of the array:

Here’s are all the files
(you can also view them online
) necessary to simulate the circuit with PSCAN. I/O of this T flip-flop was optimized for array integration, to interface it with other RSFQ cells a special two-stage JTL is required (the parameters of this JTL can be found in the netlist files referenced above).

Waveforms

Here U(/T1/J0) (the orange line in the upper window) is the voltage
across the junction J0 in T1 (the first T flip-flop of the array), and
U(/T1/J3) is the voltage across J3 in the same cell. The blue and the green
lines in the lower window show the voltages across the same junctions in
T3 – the last T flip-flop of the array. At the input of the array
we have 8 SFQ pulses and only one SFQ pulse at the output. The frequency
of the input pulses was 30 GHz.

Layout

This version was laid out for fabrication by Hypres,
Inc. Layout size is 120×80 um2.

And this is a micro-photograph of the design:

References

Historically, T flip-flop was the first single-flux-quantum device.
The early prototypes were described in:

J.P. Hurrell and A.H. Silver, “SQUID digital electronics”
in Future Trends in Supercomputer Electronics.

B.S. Deaver , Jr. et al, Eds. New York: AIP, Conf. Proc. #44, 1978,
pp. 437-447.
C.A. Hamilton and F.L. Lloyd, “100 GHz binary counter
based on dc SQUID’s”, IEEE Electron. Device Lett.

vol. 3, pp. 335-338, Nov. 1982.
V. K. Kaplunenko, V. P. Koshelets, K. K. Likharev,
V. V. Migulin, O. A. Mukhanov, G. A. Ovsyannikov, V. K. Semenov,
I. L. Serpuchenko, and A. N. Vystavkin, “Experimental Study
of the RSFQ Logic Circuits,” in: Extended Abstracts of
ISEC’87, Tokyo, pp. 127-130, Aug. 1987.

This cell and its variants are an integral part of almost all RSFQ projects,
including A/D converters, digital correlators and Time-to-Digital converters.

Recently, T flip-flops fabricated in Prof.
Lukens lab demonstrated a record operating speed for a digital circuit.
Here’s an old viewgraph
of one of the first designs and here’s another viewgraph
(available also as a Postcript
file) summarizing some of the latest results. The design made with 0.25×0.25
um2 junctions not just broke the speed record, it was also the smallest
RSFQ gate (8×9 um2) and the first one to utilize self-shunted junctions.

W. Chen, A.V. Rylyakov, Vijay Patel, J.E. Lukens, and K.K. Likharev
“Superconductor digital frequency divider operating up to 750 GHz”,
Appl.
Phys. Lett., vol. 73, no. 19, pp. 2817-2819, 1998